VREF=0, CMP0=0, CMP1=0, UART1=0, SPI0=0, I2C1=0, OSC=0, EWM=0, I2C0=0, MCG=0, SPI1=0, UART0=0, UART3=0, UART2=0
System Clock Gating Control Register 4
| EWM | External Watchdog Monitor Clock gate control 0 (0): Clock disabled 1 (1): Clock enabled |
| MCG | MCG clock gate control. 0 (0): Clock disabled 1 (1): Clock enabled |
| OSC | Oscillator (Mhz) Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| I2C0 | I2C0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| I2C1 | I2C1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART0 | UART0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART1 | UART1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART2 | UART2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART3 | UART3 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| VREF | VREF Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| CMP0 | High Speed Comparator0 Clock Gate Control. 0 (0): Clock disabled 1 (1): Clock enabled |
| CMP1 | High Speed Comparator1 Clock Gate Control. 0 (0): Clock disabled 1 (1): Clock enabled |
| SPI0 | SPI0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| SPI1 | SPI1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |